1. Field of the Invention
The present invention relates to radar and sonar systems. More specifically, the present invention relates to systems and methods for simulating targets for testing radar and sonar systems.
2. Description of the Related Art
In the radar and sonar fields, target returns arc simulated to test hardware and software associated with the system. Three essential vectors must be generated in order to simulate a target: range, velocity, and acceleration. These three vectors must be stored and recalculated at a very high rate (e.g., every 4 microseconds) in order to meet today""s radar and sonar requirements. This problem is multiplied by the fact that each target must be kept track of separately and with considerable accuracy (e.g., plus or minus one foot of error) over a long period of time. Previously, these calculations were performed in software.
Unfortunately, new radar and sonar modes require the calculations to be performed at the high rate for each target being simulated. With the multiple target processing capability of current systems, this presents a significant burden for software based simulation systems. Accordingly, software based systems tend to create simulated target returns which suffer from noncoherent jumps in both the time and frequency domains. Unfortunately, current radars require very coherent Doppler s changes in the simulated targets to perform synthetic aperture radar (SAR) type processing.
Hence, fast returns are required to adequately test modem high performance radar systems with respect to rapidly moving targets and smooth returns are desired to coherently and accurately model targets to avoid the creation of discrepancies in die accumulator of the system. As a result, prior simulators have had difficulty meeting the coherency and speed requirements of current systems.
In addition, current radar systems generally use a stream of pulses consisting of a large number of identical and consistently timed encoded packets. These packets can be further described as ambiguous or unambiguous in nature. For a packet to be unambiguous it must be transmitted to the target and received back from the target before the next pulse is transmitted. The pulse is said to be ambiguous if it has not been received before the next pulse is transmitted.
In many cases there are a large number of ambiguous pulses in route to and from a target. Previously each packet was time tagged and stored in FIFO memory so that each pulse could be accounted for and calculated separately. This required time tagging circuits, first-in/first-out (FIFO) memory, control circuits, and identification and comparison circuits.
Hence, one of the disadvantages of the prior approach lies in the complex and intolerant circuit design required by conventional teachings. In addition, conventional radar target simulation circuits had large bus and bandwidth requirements, zero tolerance for error, and no practical recovery mechanism short of reset.
Further, simulators designed in accordance with conventional teachings must typically be reset to recover from any data which might become skewed in the FIFO memory. This process tends to drop coherent RF pulse outputs.
In short, target simulation circuits designed in accordance with conventional teachings typically required a large number of discrete logic circuit elements, were considerably complex, offered no other usable features and presented numerous service and maintainability issues.
Hence, a need exists in the art for systems and techniques for creating fast, smooth virtual target motion in a simulated target environment without the large number of discrete logic circuit elements and complex problematic circuits required by prior designs.
The need in the art is addressed by the automated target simulator of the present invention. The inventive simulator includes a circuit for generating current parameters with respect to a simulated target in response to a plurality of initial values with respect thereto.
In the illustrative embodiment, the initial values include range, velocity, and acceleration and are stored in first, second and third registers accordingly. In the best mode, the invention is implemented in a field-programmable gate array having a first circuit responsive to the acceleration value stored in the first register for accumulating a term representing acceleration of the simulated target and providing an output with respect thereto. In the best mode, a fourth register is included for storing an acceleration correction value. The acceleration correction value is used by the first circuit in the accumulation of the acceleration term. The first circuit accumulates acceleration for a given time period by adding an acceleration value from a previous time period to the acceleration correction value.
The gate array further includes a second circuit responsive to the velocity value stored in the second register and the acceleration term for accumulating a term representing the velocity of die simulated target and providing an output with respect thereto. The second circuit accumulates velocity for a given time period by adding a velocity value for a previous time period to a product of acceleration for the previous time period and a period of time xcex94t.
A third circuit is included which is responsive to the range value stored in the third register and the velocity term for accumulating a term representing the range of the simulated target and providing an output with respect thereto. The third circuit accumulates range for a given time period by adding a range value from a previous time period to a product of a velocity value from the previous time period and the period of time xcex94t.
The inventive target simulator also includes a circuit for generating a simulated return from the simulated target. The circuit for generating a simulated return includes logic for determining whether a simulated pulse train to be received is ambiguous or unambiguous and adjusting the pulse repetition rate of the pulse train accordingly. The range delay circuit of the present invention calculates the initial time that a packet needs to make the trip to and from the target. Then, in the ambiguous case, the delay only calculates how long it takes between pulses to arrive rather than the entire round trip. When the round trip distance and the ambiguous time are identical, the circuit calculates both ambiguous and unambiguous signals and outputs the return of whichever type arrives first. After the initial rate is calculated then the shortest calculation between the ambiguous and unambiguous pulses determines the timing for the next returned pulse. There is no race condition because the termination comparisons are a logical OR circuit.
In the best mode, the adjustment in die pulse repetition rate is accomplished within a field programmable gate array. The inventive circuit further includes logic for adjusting the simulated return for simulating movement relative to the simulated target. The inventive simulator uses a simple tolerant circuit that recovers automatically and immediately and has far fewer circuit elements than conventional designs.